1. Technical Field
Exemplary embodiments relate to nonvolatile memory devices. In particular, exemplary embodiments are concerned with phase change memory devices, layout structures thereof, and fabrication methods thereof.
2. Related Art
One type of phase change random access memory (hereinafter, referred to as “PRAM”) is a nonvolatile memory device that exhibits different resistivities for different corresponding solid state phases in which the solid state phases can be interchanged by carefully controlling the amount and/or flux of heat, usually Joule heat, imposed on these materials. A typical phase changeable material often comprises a chalcogenide compound consisting of germanium (Ge), antimony (Sb) and tellurium (Te). Typical phase changeable materials transitionally interchange between into a disordered amorphous to an ordered crystalline solid state driven by imposing Joule heat conditions. The disordered amorphous state usually is arbitrarily assigned to logical data “1” and the ordered crystalline state is assigned to logical data “0”. Alternately the disordered amorphous state can be arbitrarily assigned to logical data “0” and the ordered crystalline state can be assigned to logical data “1”.
A memory cell of a PRAM is typically composed of a variable resistor and a switching element. The variable resistor is made of a phase changeable material coupled between a word line and a bit line. The switching element is used to selectively drive the variable resistor.
Usually in PRAM devices, word lines are provided in a form of junction regions in a semiconductor substrate and bit lines are provided in a form of wiring. The switching elements are often times diodes or metal-oxide-semiconductor (MOS) transistors.
It is well known that a word line of a junction region usually exhibits a very large resistance relative to another line pattern having the same length. Further, as the number of memory cells coupled to the word line of junction region increase, so does the rate of word line delay increases. This problem is especially aggravated with an increase of integration density of the PRAM, and as a result the word line delay of PRAMs is prone to becoming excessively large.
Referring to FIG. 1, in order to lessen a voltage delay brought about by an increase of resistance on a word line WL of junction region, a strapping line ST_WL for applying a uniform voltage to memory cells coupled to the word line WL is formed over bit lines BL.
This strapping line ST_WL is usually made of a relatively high conductivity metal and is electrically connected to the word line WL of junction region through a contact CT such as contact plug or stud. In FIG. 1, PA denotes a peripheral area and CA denotes a cell area.
However, since the strapping line ST_WL is disposed over the bit lines BL, the height of the contact CT increases by a distance between the word line WL of junction region and the strapping line ST_WL. Such an increase of the contact height causes a signal path to exhibit an undesirable delay and makes the word line resistance increase.
Furthermore, as aforementioned, the contact CT must be provided for electrically connect (i.e., Ohmic contact) the strapping line ST_WL with the word line WL of junction region. In this structural configuration, since the contact CT has to occupy a space in a cell area CA and since an interval is required between the contact CT and a bit line contact 30 that electrically connects the bit line BL with a phase changeable material 20, then this structural configuration consequently results in enlarging a cell size of the PRAM.